Technology
Discover how AI-native atomic layer etching is enabling the next generation of logic, memory, and photonic devices.
The limits of conventional etch
Below 3nm, the workhorse hits a wall.
For decades, Reactive Ion Etching (RIE) has been the workhorse of semiconductor patterning. It is fast, well-understood, and deeply embedded in every major fab's process flow. But as device geometries push below 3nm, RIE is hitting a physical wall.
Continuous plasma bombardment cannot distinguish between the layer you want to remove and the one beneath it. At the dimensions that sub-3nm logic, 300+ layer NAND, and vertical channel DRAM demand, that lack of selectivity translates directly into sidewall damage, CD variation, and yield loss. The precision requirement has outgrown the tool.
What is Atomic Layer Etch?
The mechanics of self-limiting etch cycles.
Atomic Layer Etch replaces continuous plasma bombardment with a self-limiting, sequential process that removes material one atomic monolayer at a time. Each cycle is inherently self-stopping – it physically cannot over-etch. The result is angstrom-level repeatability that no continuous etch process can match.
A standard ALE process achieves this precision by strictly separating surface modification from material removal. First, a reactive gas chemically alters just the top atomic layer of the substrate, leaving the underlying bulk structure completely untouched. Next, an inert ion bombardment selectively sweeps away only that modified layer, resetting the surface for the next cycle.
The 4-step ALE cycle
Two modes of ALE
ALE is not a single process – it is a family of techniques. The two principal modes serve different manufacturing needs:
Directional (Anisotropic) ALE
Uses low-energy directional ion bombardment to remove material preferentially in the vertical direction. Used for fin patterning, gate spacer trim, contact holes, and post-EUV LER smoothing.
Conformal (Isotropic) ALE
Removes material uniformly in all directions regardless of surface orientation. Used for GAA SiGe nanosheet release, 3D NAND staircase etch, high-k dielectric recess, and photonic waveguide smoothing.
AAT's platform supports both modes in a single chamber. That is not the industry norm – it is a significant architectural advantage.
Where ALE is now a manufacturing requirement
ALE has crossed from research technique to production necessity across four of the most important segments in semiconductor manufacturing:
- 01Advanced Logic (sub-3nm GAA)GAA nanosheet transistors require isotropic ALE to selectively remove sacrificial SiGe layers with selectivity ratios above 100:1 to silicon. No substitute process exists.
- 023D NANDAs stacks exceed 300 layers, damage removal and selective recess inside high-aspect-ratio channel holes require atomic-scale precision that RIE cannot deliver.
- 03DRAMThe transition to vertical channel transistors and 3D DRAM introduces etch steps — buried bitlines, capacitor trench finishing, gate recess – that demand ALE's self-limiting depth control.
- 04Silicon PhotonicsWaveguide sidewall roughness is the primary performance limiter in photonics. ALE is the only process that smooths surfaces to sub-nanometer roughness at production-relevant cycle times.
Our approach
Most ALE tools on the market today are conventional RIE platforms with ALE added as a module. They are constrained by an architecture built for a different process entirely.
AAT built its platform for ALE from day one with AI-native process control integrated into the hardware, not bolted on as an analytics layer. The result is a system that delivers true self-limiting etch behavior at cycle times that make atomic precision viable in high-volume manufacturing.
RIE platform · ALE bolted on as a module
Built for ALE from day one · AI-native in hardware